Many X-ray spectroscopy applications, especially on synchrotrons, require detectors which perform well at high count rates (several Mcps). As well as being a fundamental feature of SDD design, high rate capability is dependent on the whole detector system, including the pulse processor. A low capacitance charge collection and integration stage is very important to enable the detector system to be operated successfully in the high rate regime. RaySpec SDD detectors are equipped with either a low capacity FET or a MOS ASIC (‘CUBE’) device.
The chart above show the improved resolution at short Peaking Times (conventional pulse processors) offered by the CUBE ASIC device compared to a JFET (same SDD sensor), where resolutions <160eV can be achieved with input count rates >1Mcps.